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Data Path Interface (DPI) to Utopia Level 1 Translation Device
Features
! ! ! ! ! !
IDT77010
Theory of Operation
UTOPIA receive cells are transferred to the DPI-4 interface one cell at a time. The DPI-4 clock rate is twice the frequency of receive UTOPIA clock. DPI-4 transmit cells are transferred to the UTOPIA transmit bus one cell at a time. Transmit flow control is used to match the transmit cell rate to the PHY's transmit cell rate. Control cells are inserted and decoded by the control cell decoder. The control cells are filtered and will not be transferred to the UTOPIA transmit bus. The control cell decoder block identifies the control cells and signals the Utility Bus Interface to execute the commands. For a Utility bus write command cell, the Utility bus does a one byte write to the specified Utility bus address. For a Utility bus read command cell, the Utility bus reads one byte from the specified Utility bus address and loads this byte to the Cell Generator logic. The Cell Generator makes a request to the receive cell arbiter to process the cell, and generates a status cell if no UTOPIA receive cell is detected. A status cell is a complete ATM cell generated and loaded to the Receive DPI-4 I/F logic. A receive cell on the DPI-4 bus is either an ATM cell from the receive UTOPIA bus or a status ATM cell locally generated. Internally generated ATM cells are output to the Receive DPI-4 Interface only when there are no UTOPIA Receive cell. Figure 2 below shows the device data flow.
Single chip ATM Layer UTOPIA Level 1 to 4-bit DPI interface. Supports ATM Forum UTOPIA Level 1 interface. Supports ATM device interface in Cell mode. Capable of full-duplex operation up-to 160 Mbps. Utility bus interface to access PHY registers. In-stream control to access PHY registers.
Description
The 77010 interfaces a UTOPIA PHY device to a device that uses a Data Path Interface (DPI). Examples of PHY devices may include the IDT77105, and the IDT77V400 Switching Memory is an example of a component that utilizes a DPI interface. Figure 1 illustrates a typical application using the IDT77010. The UTOPIA level 1 bus interface runs at speeds up to 155 Mbps, with the DPI-4 interface capable of full duplex operation at 160 Mbps. In-stream programming is used to read and write to the PHY registers, with the Control Cells being generated from a remote controlling agent. The Control Cells are used to configure, control and retrieve status of the PHY device.
Block Diagram
OC-3 or STS-3 UTOPIA L1 Receive OC-3 PHY IDT77010 UTOPIA L1 UTOPIA L1 Transmit to DPI I/F Utility bus Switching Memory DPI Receive
4 4
DPI Transmit
" " "
" " "
IDT77V400
.
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Figure 1 Typical IDT77010 Application
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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IDT77010
Block Diagram
8 Rx UTOPIA Interface Cell MUX Rx DPI-4 Interface 4
UTOPIA Interface
No Rx cell detector/ arbiter 8 Tx UTOPIA Interface
Cell Generator 4 Control cell filter Tx DPI-4 Interface
DPI-4 Interface
8 Utility Bus Interface Control cell Decoder SysClk/2 SYSCLK
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Figure 2 Functional Block Diagram
Pin Configuration1,2
GND TxLED PHYCS PHYRST VCC GND WRITE READ PHYINT ADD/DATA0 ADD/DATA1 ADD/DATA2 ADD/DATA3 VCC GND ADD/DATA4 ADD/DATA5 ADD/DATA6 ADD/DATA7 VDD
INDEX VDD TSOC TXPRTY TXDATA7 TXDATA6 TXDATA5 GND VCC TXDATA4 TXDATA3 TXDATA2 TXDATA1 TXDATA0 GND VCC TCLK TCLAV TENB CONT_A GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
IDT77010 PQFP TOP VIEW3
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
GND ALE RSOC VCC GND RXDATA RXDATA RXDATA RXDATA RXDATA RXDATA RXDATA VCC GND RXDATA RCLK RCLAV RENB RxLED VDD
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1.
All power pins must be connected to the appropriate power supply. VCC pins to 5.0V 0.25V; VDD pins to 3.3V 0.3V. pins must be connected to ground supply. This text does not indicate orientation of the actual part-marking.
2.All GND 3.
VDD CONT_B RST LCRST DRXDATA3 DRXDATA2 DRXDATA1 DRXDATA0 SYSCLK GND VDD DRXCLK DRxFRM DTXDATA3 DTXDATA2 DTXDATA1 DTXDATA0 DTXFRM DTXCLK GND
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Pin Definitions
Signal Name SysClk RST LCRST CONT_A CONT_B RxLED TxLED READ WRITE ALE Add/Data0 Add/Data1 Add/Data2 Add/Data3 Add/Data4 Add/Data5 Add/Data6 Add/Data7 PHYCS PHYINT PHYRST RCLK RSOC RENB RCLAV RxData0 RxData1 RxData2 RxData3 RxData4 RxData5 RxData6 29 23 24 19 22 42 79 73 74 59 71 70 69 68 65 64 63 62 78 72 77 45 58 43 44 46 49 50 51 52 53 54 Pin Number Input/ Output I I I O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O O I O O I O I I I I I I I I Description System Clock. All the device circuits are synchronized to this clock. System Reset. When low the 77010 and the PHY are reset. This is used as a global line card reset where all the RST signals from all line cards are connected together. Line Card reset. When low the 77010 and the PHY are reset. This is a local line card reset used to reset a specific 77010 and PHY on a specific line card. Output Control Pin A. This pin is controlled by a receive control cell. Default output = low. Output Control Pin B. This pin is controlled by a receive control cell. Default output = low. Active low. When low a receive cell is being transferred. This pin may be used for receive activity LED. Active low. When low a transmit cell is being transferred. This pin may be used for transmit activity LED. Utility bus read signal. Utility bus write signal. Utility bus address latch enable. Used for latching the address on the address phase of the Add/Data bus. Utility bus multiplexed address and data bus. Utility bus multiplexed address and data bus. Utility bus multiplexed address and data bus. Utility bus multiplexed address and data bus. Utility bus multiplexed address and data bus. Utility bus multiplexed address and data bus. Utility bus multiplexed address and data bus. Utility bus multiplexed address and data bus. Utility bus PHY chip select. Utility bus PHY interrupt signal
Utility bus PHY reset.
UTOPIA bus receive clock. UTOPIA bus receive start of cell. UTOPIA bus receive enable. UTOPIA bus receive cell available. UTOPIA bus receive data bit. UTOPIA bus receive data bit. UTOPIA bus receive data bit. UTOPIA bus receive data bit. UTOPIA bus receive data bit. UTOPIA bus receive data bit. UTOPIA bus receive data bit.
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IDT77010 Signal Name RxData7 TENB TCLK TCLAV TSOC TxData0 TxData1 TxData2 TxData3 TxData4 TxData5 TxData6 TxData7 TxPrty DTxClk DTxFRM DTxData0 DTxData1 DTxData2 DTxData3 DRxClk DRxFRM DRxData0 DRxData1 DRxData2 DRxData3 VCC VDD GND 55 18 16 17 2 13 12 11 10 9 6 5 4 3 39 38 37 36 35 34 32 33 28 27 26 25 Pin Number Input/ Output I O O I O O O O O O O O O O O I I I I I O O O O O O UTOPIA bus receive data bit. UTOPIA bus Transmit enable. UTOPIA bus transmit clock. UTOPIA bus transmit cell available. UTOPIA bus transmit start of cell. UTOPIA bus transmit data bit. UTOPIA bus transmit data bit. UTOPIA bus transmit data bit. UTOPIA bus transmit data bit. UTOPIA bus transmit data bit. UTOPIA bus transmit data bit. UTOPIA bus transmit data bit. UTOPIA bus transmit data bit. UTOPIA bus transmit data parity bit. DPI-4 bus transmit clock. 3.3V Interface. DPI-4 bus transmit start of frame. 3.3V Interface. DPI-4 bus transmit data bit. 3.3V Interface. DPI-4 bus transmit data bit. 3.3V Interface. DPI-4 bus transmit data bit. 3.3V Interface. DPI-4 bus transmit data bit. 3.3V Interface. DPI-4 bus receive clock. 3.3V Interface. DPI-4 bus receive start of frame. 3.3V Interface. DPI-4 bus receive data bit. 3.3V Interface. DPI-4 bus receive data bit. 3.3V Interface. DPI-4 bus receive data bit. 3.3V Interface. DPI-4 bus receive data bit. 3.3V Interface. 5.0V Power Supply Pins. 3.3V Power Supply Pins for DPI Interface. Ground Pins. Description
8,15,48,57,67,76 Power 1,21,31,41,61 Power
7,14,20,30,40,47 GND ,56,60,66,75,80
1.All signals are 5.0V unless otherwise indicated. 2.
3.3V signals are 5.0V tolerant.
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Absolute Maximum Ratings
Symbol VCC VDD VIN IOUT TSTG Parameter 5V Digital Supply Voltage 3.3V Digital Supply Voltage Digital Input Voltage Output Current Storage Temperature Min -0.3 -0.3 VSS ____ -55 6.0 4.6 VCC + 0.5 50 140 Max V V V mA C Unit
Recommended Operating Conditions
Symbol VCC VDD VIN TA titr titf VIH VIL Parameter 5V Digital Supply Voltage 3.3V Digital Supply Voltage TTL Input Voltage Operating Temperature Input TTL rise time Input TTL fall time TTL Input High Voltage TTL Input Low Voltage Min 4.75 3.0 -0.3 0 ____ ____ 2.0 ____ Max 5.25 3.6 VCC+0.3 70 2 2 ____ 0.8 V V V C ns ns V V Unit
DC Electrical Characteristics
Symbol [ILI] [ILO] VOH VOL IDD ICC Parameter Input Leakage Current Output Leakage Current TTL Output High Voltage TTL Output Low Voltage Power Supply Current Power Supply Current Test Conditions VCC = 5.5V, VIN = 0V to VCC VOUT = 0V to VCC IOH = -4mA IOL = +4mA 155.52 Mbps 155.52 Mbps 10 10 2.4 ___ ___ ___ 77010 Min Max 10 10 ___ 0.4 60 12 Unit A A V V mA mA
Capacitance
Symbol CIN COUT CBID Parameter Input Capacitance Output Capacitance Bi-Directional Capacitance Test Conditions All Inputs All Outputs All Bi-directional Pins Min ___ ___ ___ Type 4 6 10 Max ___ ___ ___ Unit pF pF pF
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Device Interface
This 77010 uses a UTOPIA level 1 interface to receive and transmit ATM cells to and from the PHY device. It mirrors the ATM layer as shown in Figure 3 below.
DRxFRM DRxCLK DRxDATA[3:0]
RSOC RCLK RxDATA[7:0] RENB
DPI-4 3.3V Interface DTxFRM DTxCLK
RCLAV IDT77010 TxPRTY TSOC TCLK DTxDATA[3:0] TxDATA[7:0] TENB LCRST RST SYSCLK TCLAV PHYRST PHYCS PHYINT ADD/DATA[7:0] Utility Bus ALE READ WRITE RxLED TxLED CONT_A CONT_B
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UTOPIA-1 Interface
Figure 3 DPI-4 to UTOPIA 1 Interface Device
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UTOPIA Receive Interface Operation
UTOPIA cell level handshake is used to receive an ATM cell from a UTOPIA PHY device. The UTOPIA Receive Clock (RCLK) is a continuous clock generated from the System Clock (SYSCLK) and is half the frequency of the DPI Receive Clock (DRxCLK). The receive cell header, including the HEC, and payload are transferred over the Receive Data bus (RxDATA[7:0]), which is 8-bits wide. Receive Parity (RxPRTY) is not supported by the 77010, nor does it calculate the HEC in the header field. The 77010 will assert Receive Enable (RENB) low two clock cycles after detecting a high Receive Cell Available (RCLAV), if it is not executing a control cell. Refer to the UTOPIA Receive Flow Control section for description on muxing internally generated control cells with UTOPIA receive cells. Once Receive Start Of Cell (RSOC) is detected the 77010 will receive the entire cell without interruption.
Internally generated control cells should be paced so that the sum of receive UTOPIA status cells and internally generated control cells do not exceed 160 Mbps. The PHY is expected to buffer at least two receive cells for the flow control to function without the loss of a cell. Figure 4 shows the receive cell muxing with the internally generated status cells.
UTOPIA Transmit Interface Operation
UTOPIA cell level handshake is used to transfer an ATM cell to a UTOPIA PHY device. The UTOPIA Transmit Clock (TCLK) is a continuous clock generated from the System Clock (SYSCLK) and is half the frequency of the DPI Transmit Clock (DTxCLK). Two TCLK cycles after detection of a high Transmit Cell Available (TCLAV) the 77010 will assert TENB low. One TCLK cycle after TENB assertion the 77010 will assert Transmit Start Of Cell (TSOC) and the first valid byte of data. TSOC is one TCLK cycle long and coincides with the first valid byte of data (TxDATA[7:0]). When the entire cell has been transferred the 77010 will sample TCLAV for cell availability. The PHY will de-assert TCLAV if it cannot accept another cell. The 77010 will continue transferring the current cell and store up to nine bytes of the next cell in its pipeline if TCLAV is de-asserted during a cell transfer. Control cells from the DPI interface are filtered and not forwarded to the transmit UTOPIA bus. Figure 5 shows UTOPIA transmit data flow.
UTOPIA Receive Flow Control
The UTOPIA data rate is higher than the cell rate on the transport media. This provides additional bandwidth for the insertion of control cells. The 77010 will only generate an internal control cell when RCLAV and RENB are de-asserted and a cell transfer is not taking place. When a control cell is inserted RENB is de-asserted high for 55 RCLK cycles, which prevents the PHY from transferring a cell. During this 55 clock period the 77010 inserts the control cell and sends it out to the DPI receive interface.
Line Card Interface Internally generated status cell
UTOPIA Receive Bus PHY 8
Receive DPI bus 4
No back to back Rx cell detector
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Figure 4 UTOPIA Receive Data Flow
UTOPIA Transmit bus 8
PHY
UTOPIA Interface
Control cell filter
4 to 8 Interface
Transmit DPI bus 4
TCLAV
UTOPIA Interface
DPI TxCLK Control
Transmit DPI clock
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Figure 5 UTOPIA Transmit Data Flow 7 of 21 June 24, 2002
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Input Control Cell Formatting
Control cells are generated by a remote computer and are used to configure and monitor the PHY registers. All cells having the header VPI = 0x00 hex and VCI = 0x1F hex (VCI bits 11-4) are decoded and executed as control cells by the 77010.
UTOPIA bus is at full rate. In this case it is recommended that the control cells be at least 50 cells apart.
DPI Interface Operation
Data Path Interface (DPI) is a synchronous bus interface designed to transfer ATM cells between two devices. The 77010 contains a DPI-4 bus interface, which contains a four bit wide data bus. Therefore, 107 clock cycles are required to transfer a 53 byte ATM cell. The 77010 has separate DPI-4 transmit and receive interfaces, with each requiring six signals. The signals are a clock, a start of cell marker and a four bit data bus. All signals are sampled on the rising edge of their respective clock.
Control Cell Filter Operation
All cells transferred over the DTxDATA[3:0] bus are tested to see if they are control cells.Cells containing the header VPI = 00 Hex and VCI = 1F Hex (VCI bits 11-4) are filtered as control cells and not forwarded to the TxDATA[7:0] bus. The filter ignores the GFC, PTI and CLP bits. The default control cell identifier value is 00x1F. It can be programmed to a user defined value via the Change Control Cell Address Command (see page 16).
Transmit DPI Bus Interface
The Transmit DPI Clock (DTxCLK) is generated from SYSCLK and is twice the frequency of TCLK. This clock is not continuous and is used to control data flow to the PHY device. DTxCLK is initially low and not driven until the 77010 detects a high TCLAV from the PHY device. On the rising edge of DTxCLK the 77010 samples Transmit Start of Cell (DTxFRM), which is generated by the transmitting device for one DTxCLK cycle. When DTxFRM is asserted high the 77010 will sample valid data (DTxDATA[3:0]) on the next rising edge of DTxCLK. Cell transfer will continue without interruption once it has started. When TCLAV is de-asserted low the current cell is transferred and DTxCLK goes low until another high TCLAV is detected. DTxFRM and DTxDATA[3:0] are sampled on the rising edge of DTxCLK.
Control Cell Frequency
The control cells arrive multiplexed with data cells in random combinations, and are terminated (filtered) by the 77010. The RxDATA[3:0] bus multiplexes the receive UTOPIA cells and any internally generated control cells. The control cell is ignored if a previous control cell is being executed at that time. A gap in the UTOPIA cell stream must occur before the new control cell is processed, because the UTOPIA receive cells have higher priority. Control cells may be input back-to-back. However, the second control cell will not be processed and could be dropped, even though the 77010 can filter both of them. Worst case condition is when the receive
Control ATM Cell Format
Cell Byte Number 0 0 1 1 2 3 3 3 4 5 6 7 8 Bit Number 7-4 3-0 7-4 3-0 7-0 7-4 3-1 0 7-0 7-0 7-0 7-0 7-0 Function Name GFC VPI 7-4 VPI 3-0 VCI 15-12 VCI 11-4 VCI 3-0 PTI CLP HEC Command Data A Data B reserved Bit Contents 0xX 0x0 0x0 0x0 0xYY 0x0 000'b 0'b 0x00 00-FF Hex 0x0 - 0xFF 0x0 - 0xFF 0x00 Don't care. Must be set to 0x0. Must be set to 0x0. Must be set to 0x0. Special VCI value for control and status cells. Default is 0x1F.1 Don't care. Don't care. Don't care. Don't care. Command cell byte. Parameter for control cell. Parameter for control cell. Always set to 0x00. Description
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IDT77010 Cell Byte Number . . 52
1.
Bit Number 7-0 7-0 7-0
Function Name reserved reserved reserved
Bit Contents 0x00 0x00 0x00 Always set to 0x00. Always set to 0x00. Always set to 0x00.
Description
This value can be programmed by instream control cells.
DPI Bus Data Sequence
For Transmit and Receive DPI bus in the 53 byte configuration, the following table shows the data nibble sequence.
DPI Nibble Count 0 1 2 3 4 5 6 7 8 9 10 11 ____ ____ 104 105 DPI Content GFC [3:0] VPI [7:4] VPI [3:0] VCI [15:12] VCI [11:8] VCI [7:4] VCI [3:0] PTI [2:0], CLP HEC [7:4] HEC [3:0] First data byte [7:4] First data byte [3:0] ____ ____ Last data byte [7:4] Last data byte [3:0] Comments GFC bits for the ATM cell header. First nibble to be transmitted/received. VPI bits MSB of the ATM cell header. VPI bits LSB of the ATM cell header. VCI bits MSB of the ATM cell header. VCI bits of the ATM cell header. VCI bits of the ATM cell header. VCI bits of the ATM cell header. PTI and CLP bits of the ATM cell header. HEC Most Significant nibble. HEC Least Significant nibble. First data Most Significant nibble of the ATM cell header. First data Least Significant nibble of the ATM cell header. ____ ____ Last data byte Most Significant nibble of the ATM cell. Last data byte Least Significant nibble of the ATM cell.
DTxClk (Output) DTxFRM (Input) DTxData[3:0] (Input)
0
1
2
104
105
Figure 6 DPI-4 Transmit Bus with only one cell
DTxClk (Output) DTxFRM (Input) DTxData[3:0] (Input)
105
0
1
2
3
4
102
103
104
105
0
1
2
Figure 7 DPI-4 Transmit Bus with back to back cell
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Receive DPI Bus Interface
The Receive DPI Clock (DRxCLK) is a continuous clock generated from SYSCLK and is twice the frequency of RCLK. The Receive Start of Cell marker (DRxFRM) is also generated by the 77010 and is asserted for one clock cycle prior to the first nibble of valid data (DRxDATA[3:0]). There is no flow control in the receive DPI path. It is assumed that the receiving device can accept the incoming cell. DRxFRM and DRxDATA[3:0] are sampled on the rising edge of DRxCLK.
DRxClk (Output)
DRxFRM (Output) DRxData[3:0] (Output)
0
1
2
3
4
104
105
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Figure 8 DPI-4 Receive Bus with only one cell
DRxClk (Output) DRxFRM (Output) DRxData[3:0] (Output)
105
0
1
2
3
4
102
103
104
105
0
1
2
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Figure 9 DPI-4 Receive Bus with back to back cell
Utility Bus
The Utility bus is used for accessing the internal PHY registers. An 8-bit read or write command is implemented via instream (in-band) programming to access the registers. The commands are input to the 77010 via the DPI-4 transmit path. The PHY register commands are decoded by the 77010 and executed using the Utility bus. Figure 10 shows the Utility bus interface.
UTILITY BUS PHYCS PHYINT Add/Data[7:0] IDT77010 ALE READ PHYRST WRITE
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PHY or an External device
Figure 10 Utility Bus Interface
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Utility Bus Read Operation
When the 77010 decodes the command cells for a Utility bus read operation, it drives the PHY chip select (PHYCS), Address Latch Enable (ALE),Read(READ) and the Address Data bus (Add/Data[7:0]). At the falling edge of ALE, the PHY samples the address phase of the Add/Data[7:0]. The 77010 then floats the Add/Data[7:0] bus. The PHY drives the Add/Data[7:0] bus until rising edge of PHYCS or READ. See Figure 11 below.
SYSCLK tPALE ALE tALPW
PHYCS
tPPHY tALR tRDPW
READ Add/Data[7:0]
tAAL
tALA Address Read Data from PHY tDRS tDRH 4308 drw 12
Figure 11 Utility Bus Read Operation
Utility Bus Write Operation
When the 77010 decodes the command cell for a Utility bus write operation, it drives the PHY chip select (PHYCS), Address Latch Enable (ALE), Write (WRITE), and the Address Data bus (Add/Data[7:0]). At the falling edge of ALE, the PHY samples the address phase of the Add/Data[7:0]. The PHY samples the write data byte on the Add/Data[7:0] bus at the rising edge of PHYCS or WRITE. See Figure 12 below.
SYSCLK tPALE ALE PHYCS tALPW
tPPHY
WRITE tAAL Add/Data[7:0]
tALW tALA Address Write Data to PHY
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tDWS
tDWH
Figure 12 Utility Bus Write Operation
Reply Command Cell
Interrupt Reply Cell Notification Return command cell indicating an interrupt has occurred on the Utility bus.
Command Fields Command DataA DataB 00 xx xx Field Value (Hex) Interrupt Cell Return Command See Data A and Data B Tables on page 14. See Data A and Data B Tables on page 14. Description
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Command Cells
Reset PHY Chip Command Resets the PHY device and the Utility bus. PHYRST will assert low for 16 SYSCLK cycles. This command does not generate nor return a command cell.
Command Fields Command DataA DataB 01 xx xx Field Value (Hex) Reset Phy Chip. Don't care. It may contain any number. Don't care. It may contain any number. Description
Utility Bus Write Command
Writes one byte per command cell to the Utility bus. The Utility bus is used to write to the PHY registers. This command does not generate nor return a command cell.
Command Fields Command DataA DataB 02 00 - FF 00 - FF Field Value (Hex) Write to Utility bus. Utility bus address. Utility bus data byte to be written. Description
Utility Bus Read Command
Reads one byte per command cell from the Utility bus. The Utility bus is used to read the PHY registers. This command generates a return command cell. See Reply Cell Format Table.
Command Fields Command DataA DataB 03 00 - FF xx Field Value (Hex) Read to Utility bus. Utility bus address. Don't care on command. Will return value from Data B Table. Description
Output Pin Control Command
This command controls the output pins CONT_A and CONT_B, and causes an internally generated cell. See internally generated cell format section.
Command Fields Command DataA DataB 00 01 02 03 04 xx Field Value (Hex) Description Define CONT_A and CONT_B Output State. Don't Care. Control pins output state. CONT_A CONT_B Low Low Low High High Low High High
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Status Read Command
This command reads the 77010 Revision number and the Interrupt pin state, and causes an internally generated cell. See internally generated cell format section.
Command Fields Command DataA DataB 05 xx xx Field Value (Hex) Status cell. See Data A and Data B Tables on page 14. See Data A and Data B Tables on page 14. Description
Change Control Cell Address Command
This command is used to change the control cell address. Once modified the IDT77010 will not filter old (default = 0x1Fx) values from the ATM cell stream. The command does not return a command cell.
Command Fields Command DataA DataB 06 00--FF xx Field Value (Hex) Status cell. New Control Cell Address; placed in lower byte of VCI Field Don't care. Description
Internally Generated Reply Cell Format
Internal cells are generated in response to a command cell or PHY interrupt. The cells are remotely sent and switched to the 77010. The cell format of an internally generated cell is as follows:
Cell Byte Number 0 0 1 1 2 3 3 3 4 5 6 7 8 . . 52 Bit Number 7-4 3-0 7-4 3-0 7-0 7-4 3-1 0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 7-0 Function Name GFC VPI 7-4 VPI 3-0 VCI 15-12 VCI 11-4 VCI 3-0 PTI CLP HEC Command Data 1 Data 2 reserved reserved reserved reserved Bit Contents 0x0 0x0 0x0 0x0 0x02 0x0 000'b 0'b 0x00 00-FF Hex See below See below 0x00 0x00 0x00 0x00 Always set to 0x0 Always set to 0x0 Always set to 0x0 Always set to 0x0 Special VCI value for control and status cells. Special VCI value for control and status cells. Always set to 000'b. Always set to 0. Transmit HEC byte, always set to 0x00. The PHY device generates and calculates the HEC byte. This returned cell value is the same as the command cells Command byte. For interrupt cell this byte = 00 hex. See below. See below. Always set to 0x00. Always set to 0x00. Always set to 0x00. Always set to 0x00. Description
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Internally Generated Reply Cell Table - Data A
Internally Generated Cell Type Utility Bus Read Status Read Cell Interrupt Cell Return 7-0 7 6-0 7 6-0 Data A Byte Bit Number Description Address of the Utility bus read. This bit has the value of the interrupt pin at the time of this cell's generation. Reserved. Set to 0. This bit has the value of the interrupt pin at the time of this cell's generation. Reserved. Set to 0.
Internally Generated Reply Cell Table - Data B
Internally Generated Cell Type Utility Bus Read Status Read Cell Interrupt Cell Return 7-0 7-0 7-0 Data A Byte Bit Number Description Data value of the Utility bus read. Revision number of the device. Revision number of the device.
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Symbol tCYC tCH tCL tUCYC tUCH tUCL tTOV tUTS tUTH tROV tURS tURH tDCYC tDCH tDCL tDTS tDTH tPDRD tALPW tALR tALW tRDPW tAAL tALA tDRS tDRH tDWS tDWH tWRPW tPINTS tPINTH tPALE tPPHY tPPHYR tPRCLK SCLK Cycle Time SCLK High Time SCLK Low Time
Parameter 20 8 8 50 20 20 1 10 1 1 10 1 25 9 9 6 2
77010 Min Max ____ ____ ____ ____ ____ ____ 20 ____ ____ 20 ____ ____ ____ ____ ____ ____ ____ 13 ____ 22 22 ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ 22 22 22 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Unit
UTOPIA TCLK/RCLK Cycle Time UTOPIA TCLK/RCLK High Time UTOPIA TCLK/RCLK Low Time TxDATA, TxPRTY, TENB, TSOC Output Valid from TCLK TCLAV to TCLK Setup Time TCLAV to TCLK Hold Time RENB Output Valid from RCLK RxDATA, RSOC, RCLAV to RCLKSetup Time RxDATA, RSOC, RCLAV to RCLK Hold Time DPI DTxCLK/DRxCLK Cycle Time DPI DTxCLK/DRxCLK High Time DPI DTxCLK/DRxCLK Low Time DTxFRM, DTxDATA to DTCLK Setup Time DTxFRM, DTxDATA to DTCLK Hold Time DRxCLK to DRxDATA(0-3), DRxFRM Propagation Delay ALE Pulse Width System Clock to READ Low Propagation Delay System Clock to WRITE Low Propagation Delay Read Pulse Width Address to ALE Falling Edge Setup Time Address to ALE Falling Edge Hold Time Data to rising edge of READ Setup Time Data to rising edge of READ Hold Time Data to rising edge of WRITE Setup Time Data to rising edge of WRITE Hold Time Write Pulse Width System Clock to PHYINT Setup Time System Clock to PHYINT Hold Time ALE to System Clock Propagation Delay System Clock to PHYCS Propagation Delay System Clock to PHYRST Propagation Delay System Clock to Utopia Receive Clock Propagation Delay
____ 40 ____ ____ 80 20 10 5 1 5 1 40 10 1 ____ ____ ____ ____
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IDT77010 77010 Min ____ ____ ____ ____ ____ ____ ____ 10 3 20 10 10 19 9 22 22 ____ ____ Max ns ns ns ns ns ns ns ns ns
Symbol tPTCLK tPDRxCLK tPDTxCLK tPRLED tPTLED tPCNTA tPCNTB tPRSTS tPRSTH
Parameter System Clock to Utopia Transmit Clock Propagation Delay System Clock to DPI Receive Clock Propagation Delay System Clock to DPI Transmit Clock Propagation Delay System Clock to RxLED Propagation Delay System Clock to TxLED Propagation Delay System Clock to CONT_A Propagation Delay System Clock to CONT_B Propagation Delay Rising Edge of RST and LCRST to Rising Edge of System Clock Setup Time Rising Edge of RST and LCRST to Rising Edge of System Clock Hold Time
Unit
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IDT77010
System Clock Timing Waveform
tCYC SYSCLK tCH tCL
4308 drw 14
UTOPIA Transmit Timing Waveform
tUCYC TCLK tTOV TxDATA(0-7), TENB, TSOC tUTS TCLAV 4308 drw 15 tUTH tUCH tUCL
UTOPIA Receive Timing Waveform
RCLK tROV RENB tURS tURH
RxDATA(0-7), RSOC, RCLAV
4308 drw 16
DPI Transmit Timing Waveform
tDCYC DTxCLK tDCH DTxFRM, DTxDATA(0-3)
4308 drw 17
tDCL tDTS tDTH
DPI Receive Timing Waveform
DRxCLK tPDRD DRxFRM, DRxDATA(0-3)
4308 drw 18
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IDT77010
System Clock to UTOPIA Receive Clock Propagation Delay
SYSCLK tPRCLK RCLK
4308 drw 19
System Clock to UTOPIA Transmit Clock Propagation Delay
SYSCLK tPTCLK TCLK
4308 drw 20
System Clock to DPI Receive Clock Propagation Delay
SYSCLK tPDRxCLK DRxCLK
4308 drw 21
System Clock to DPI Transmit Clock Propagation Delay
SYSCLK tPDTxCLK DTxCLK
4308 drw 22
System Clock to RxLED Propagation Delay
SYSCLK
tPRLED
RxLED
4308 drw 23
System Clock to TxLED Propagation Delay
SYSCLK
tPTLED
TxLED
4308 drw 24
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IDT77010
System Clock to Count_A Propagation Delay
SYSCLK
tPCNTA
CONT_A
4308 drw 25
System Clock to Count_B Propagation Delay
SYSCLK
tPCNTB
CONT_B
4308 drw 26
System Clock to PHYRST Propagation Delay
SYSCLK
tPPHYR
PHYRST
4308 drw 27
System Clock to PHYINT Setup and Hold Times
SYSCLK
tPINTS tPINTH
PHYINT
4308 drw 28
System Clock to RST and LCRST Setup Time
SYSCLK
tPRSTH tPRSTS
RST, LCRST
4308 drw 31
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IDT77010
Package Information
Plastic QFP 80pin Body size 12 x 12 x 1.4mm (QFP14)
HD D 60 61 41 40
f E b HE
Index 80 1 2
A2
21 20 R1 R
Amax
A1
3 L2 L1 L C
4308 drw 29
Symbol
Dimension in Millimeters Min Norm 12 12 0.1 1.3 0.13 0.1 0o 0.3 0.5 1 0.5 13.6 13.6 14 14 14.4 14.4 (0.536) (0.536) 1.4 0.5 0.18 0.125 0.28 0.175 10o 0.7 (0.006) (0.004) (0o) (0.012) 1.5 (0.052) 12.1 12.1 1.7 Max Min (0.469) (0.469)
Dimension in Inches1 Norm (0.472) (0.472) (0.004) (0.055) (0.020) (0.007) (0.005) (0.020) (0.039) (0.020) (0.551) (0.551) (0.566) (0.566) (0.011) (0.006) (10o) (0.027) (0.059) Max (0.476) (0.476) (0.066)
E D A A1 A2 f b C q L L1 L2 HE HD q2 q3 R R1
1.
11.9 11.9
0.2 0.2
for reference
(0.008) (0.008)
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IDT77010
Ordering Information
IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range
Blank
Commercial (0 Degrees C to +70 Degrees C)
PQF
PQFP (80-pin)
155
4-bit Port Bandwidth in Mbps
L
Low Power
77010
UTOPIA 1 TO DATA PATH INTERFACE (DPI) TRANSLATION DEVICE
4308 drw
Data Sheet Document History
4/02/99 5/18/99 6/24/99 7/06/99 2/12/01 6/24/02 Changed format Changed tDTH from 6ns to 2ns, changed tALPW from 20ns to 40ns, added TxPRTY prop. delay. Changed tDCH and tDCL from 8ns to 9ns, added tTOV and tROV min of 1ns. Changed tPTCLK from 11ns to 20ns to match RCLK. Changed to Final. Made general corrections. No parameters changed. Added drawing 4308d31, System Clock to RST and LCRST Setup Time. Added tPRSTS and tPRSTH timing to timing parameters table. Changed e-mail URL from atmhelp@idt.com to switchstarhelp@idt.com.
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com
for Tech Support: email: switchstarhelp@idt.com phone: 408-492-8208
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